I don't see how eliminating an in-between pci-express controller to communicate between the two cores could possibly be a bad thing... or consume more power? If anything, one less chip means less power, less latency? Possible increase in peformance, less complicated PCB design?
I don't think it's possible to eliminate the PLX switch since it's needed to for the GPUs to share the PCI-E bus.
It'd be nice to see sideport return if it can really improve CF performance, but we would have to at least wait until ATI's next-gen since it was cut from Cypress.